Yields in IC device fabrication processes are often impacted by defects resulting from alignment variations of subsurface layers or patterns, particulate contaminants, or defects in the substrate material itself. FIGS. 1, 2A, and 2B show repetitive electronic circuits 10 of an IC memory device or workpiece 12 that are typically fabricated in rows or columns to include multiple iterations of redundant circuit elements 14, such as spare rows 16 and columns 18 of memory cells 20. With reference to FIGS. 1, 2A, and 2B, circuits 10 are also designed to include particular laser severable circuit links 22 between electrical contacts 24 that can be removed to disconnect a defective memory cell 20, for example, and substitute a replacement redundant cell 26 in a memory device such as a DRAM, an SRAM, or an embedded memory. Similar techniques are also used to sever links to program a logic product, gate arrays, or ASICs.
Links 22 are designed with conventional link widths 28 of about 1.0 micron, link lengths 30, and element-to-element pitches (center-to-center spacings) 32 of about 1.5 microns or less from adjacent circuit structures or elements 34, such as link structures 36. Link dimensions and pitches are continually being reduced by device manufacturers. Although the most prevalent link materials have been polysilicon and like compositions, memory manufacturers have more recently adopted a variety of more conductive metallic link materials that may include, but are not limited to, aluminum, copper, gold nickel, titanium, tungsten, platinum, as well as other metals, metal alloys such as nickel chromide, metal nitrides such as titanium or tantalum nitride, metal suicides such as tungsten silicide, or other metal-like materials.
Circuits 10, circuit elements 14, or cells 20 are tested for defects. The links to be severed for correcting the defects are determined from device test data, and the locations of these links are mapped into a database or program. Laser pulses have been employed for more than 20 years to sever circuit links 22. FIGS. 2A and 2B show a laser spot 38 of spot size diameter 40 impinging a link structure 36 composed of a link 22 positioned above a silicon substrate 42 and between component layers of a passivation layer stack including an overlying passivation layer 44 (shown in FIG. 2A but not in FIG. 2B) and an underlying passivation layer 46 (shown in FIG. 2B but not in FIG. 2A). FIG. 2C is a fragmentary cross-sectional side view of the link structure of FIG. 2B after the link 22 is removed by the laser pulse.
The prior art uses laser pulses comprised of only a single laser wavelength for semiconductor device link processing. A single laser pulse at a 1064 nm or 1047 nm wavelength has been widely used for semiconductor memory chip link on-the-fly processing, which entails severing individual links with a single pulse for each link while not stopping beam positioner motion. A laser pulse at 1320 nm became preferable later in metal link processing because it caused less damage to a silicon substrate. Link processing with a UV laser pulse also has been proposed and practiced. Double pulse processing of fat (i.e., thick) copper links has been attempted by a few users. All of the laser pulses used were at the same wavelength.
Wavelengths advantageous for minimizing silicon substrate damage and enhancing a process window are near 1300 nm, as disclosed in U.S. Pat. No. 5,265,114, which is assigned to the assignee of this patent application. However, the smallest practical laser beam spot size at 1300 nm is about 1.7 microns. The ever-shrinking feature size or link dimensions of semiconductor memory chips demand a laser beam spot size of 1.4 microns and smaller. Using a short wavelength in the UV spectral range, as disclosed in U.S. Pat. No. 6,057,180, which is assigned to the assignee of this patent application, can deliver the small beam spot size needed and cut through an overlying passivation layer but requires that the passivation material absorb the UV wavelength to protect the silicon substrate. Moreover, the link structure design should cooperate with the underlying passivation layer structure to inflict only minor damage to the underlying passivation material. Using a short wavelength in the green/visible range would carry a high risk of damage to the silicon substrate because of its high absorption of wavelengths in the green/visible range.
What is desired for purposes of semiconductor device micromachining is a series of special laser pulses, each with an energy profile comprised of different laser wavelengths at different times within the energy profile sequenced to the different processing characteristics of the layers in the multi-layer structure. One such energy profile sequence would be a first part of the laser pulse energy profile at a UV or green wavelength to best process the overlying passivation layer and top part of the link material, followed by a second part of the laser pulse energy profile at a 1.3 micron wavelength to clear the remaining link material while limiting risk of damage to the underlying passivation layer and silicon wafer substrate.